Work

All Projects

A collection of hardware, embedded systems, software, and data projects.

Senior Capstone
Underground Wireless Sensor Network
Alpha Metallurgical Resources — University of Alabama
RF / Wireless Embedded Systems Field Testing

Selected by Alpha Metallurgical Resources to design a wireless sensor network for real-time data transmission in underground coal mining environments as part of the University of Alabama Senior Capstone Program.

  • Designed and implemented a low-latency (<5 ms), high-throughput (~100 Mbps) dual-band (2.4 GHz / 5 GHz) network under harsh underground conditions
  • Ensured reliable communication in non-line-of-sight tunnel environments
  • Collaborated with industry engineers, faculty advisors, and a multidisciplinary team of four on system architecture, component selection, and deployment strategy
  • Conducted on-site testing in an active underground mine, identifying and mitigating challenges including RF interference, airlocks, and competing mesh networks
  • Validated system performance with zero packet loss in constrained underground environments
Capstone team underground with American flag
Team photo underground
Underground mine tunnel with equipment
Tunnel with deployed equipment
Testing laptop setup in mine
On-site testing at belt head
Mine map with test locations
Mine schematic — test locations
FPGA / SystemVerilog
FPGA Calculator System
Basys3 — Digilent / Xilinx
SystemVerilog Basys3 Vivado 100 MHz

Designed a modular calculator on the Digilent Basys3 FPGA in SystemVerilog. The architecture features a hierarchical FSM control unit for input parsing and operation sequencing, paired with a synchronous datapath that performs the actual arithmetic with clean control/datapath separation.

  • Designed modular SystemVerilog architecture with hierarchical FSM control
  • Implemented synchronous datapath and control separation for clean design
  • Developed seven-segment display driver with multiplexed timing logic
  • Simulated and validated design in Vivado; synthesized for Basys3 at 100 MHz
Basys3 FPGA board
Digilent Basys3 FPGA
Data Processing
Lake Mapping & Sonar Data Processing
4 lake systems across New York and Alabama
ReefMaster Sonar GPS Bathymetry

Collected and processed sonar log data to generate detailed bathymetric maps of lake environments. Applied GPS offset correction and signal filtering in ReefMaster, generated AT5-compatible overlays for marine electronics systems, and produced side-scan mosaics and bottom composition models.

  • Collected raw sonar log data from boat-mounted transducers across multiple lake systems
  • Applied GPS offset correction and signal filtering in ReefMaster for accurate depth contours
  • Generated AT5-compatible overlays for Humminbird and other marine electronics
  • Produced side-scan sonar mosaics and bottom composition models
Cayuga Lake sonar overlay
Cayuga Lake, NY
Oneida Lake sonar overlay
Oneida Lake, NY
Oneida Lake sonar detail
Oneida Lake, NY (detail)
Lake Holt sonar overlay
Lake Holt, Tuscaloosa AL
Riverview sonar overlay
Riverview, Tuscaloosa AL
Embedded Systems
STM32 / Embedded C
Digital I/O & 7-Segment Display Controller
ECE 487/587 Lab 2 — STM32 Nucleo L476RG
C (Embedded) STM32CubeIDE GPIO UART

Built a complete digital I/O system on an STM32 Nucleo board, interfacing a toggle switch, on-board push button, and a 7-segment LED display wired on a solderless breadboard. The firmware cycles hex digits 0-F on the display, then switches between two operating modes based on the toggle switch state.

  • Configured GPIO pins via STM32CubeMX and drove a 7-segment display using a look-up table for segment encoding
  • Implemented dual-mode operation: heartbeat display (500ms blink) when idle, hex button-press counter when active
  • Integrated UART serial output for real-time status messages ("Counting started", "Current count X")
  • Implemented software debouncing for reliable switch and button input
STM32 Nucleo wired to breadboard with 7-segment display
Nucleo + breadboard + 7-seg wiring
FPGA & Digital Logic
📡 FPGA / VHDL
UART Transmitter

Hardware implementation of the UART serial communication protocol on an FPGA. Handles baud-rate generation, start/stop bit framing, and reliable asynchronous data transmission at the register-transfer level.

VHDL Xilinx Vivado Serial Comms FPGA
🔁 FPGA / VHDL
Elevator Control System

Finite State Machine (FSM) design for a multi-floor elevator controller. Manages floor requests, direction logic, and door control using sequential digital logic synthesized on an FPGA board.

VHDL FSM Design Xilinx Vivado Sequential Logic
🪙 FPGA / VHDL
Vending Machine FSMD

A Finite State Machine with Datapath (FSMD) modeling a vending machine. Combines control logic (FSM) with arithmetic datapath units to process coin inputs and dispense products correctly.

VHDL FSMD Datapath Design FPGA
Software & Algorithms
🗂️ Python / Algorithms
Data Structures from Scratch

Custom implementations of core data structures in Python — including a HashMap with collision handling & dynamic rehashing, a Heap with percolation logic, a Binary Search Tree, and a Graph with adjacency list representation.

Python HashMap Heap Graph BST
⚡ Python / Algorithms
Dynamic Programming Suite

Algorithm implementations exploring dynamic programming, BFS/DFS on matrices and graphs, backtracking, and classic problems like Fibonacci with memoization and tabulation approaches.

Python Dynamic Programming BFS / DFS Backtracking
🤖 Python / Automation
SkyblockMacro

A Python GUI automation tool built with Tkinter and pynput (~4,000 lines). Features multi-threaded macro execution with start/stop controls, keyboard and mouse automation, and iterative refinement across multiple versions.

Python Tkinter pynput Threading GUI